1. Field of the Invention
The present invention is generally directed to the field of semiconductor processing, and, more particularly, to reducing the thickness of previously-formed process layers.
2. Description of the Related Art
Within the semiconductor industry there is a constant drive to reduce the feature size of semiconductor devices, e.g., transistors. Reductions in feature size may lead to increased performance of the device, i.e., it may operate at greater speeds. Additionally, reducing the feature size of the semiconductor devices may increase profitability, in that, all other things being equal, smaller feature sizes may result in more chips being manufactured on the same size substrate or wafer.
As feature sizes are reduced, e.g., as channel lengths are reduced, a corresponding reduction in size or scaling of other parts of the semiconductor device may also be required. For example, in metal oxide field effect transistors, the thickness of the gate insulation layer may have to be reduced to optimize the performance of the semiconductor device. However, in forming a process layer, such as a gate insulation layer, modem forming methods and devices may not be able to directly form the process layers as thin as is desirable for the finished semiconductor device. Thus, there is a need for a method and apparatus that may be used to reduce the thickness of the previously-formed process layers.
The present invention is directed to a semiconductor device that solves some or all of the aforementioned problems and a method for making same.